EDA Connect 2025 β SystemVerilog Training & Hackathon
We are pleased to announce that EDA Connect 2025 will feature a SystemVerilog training session on March 13, 2025, followed by a Hackathon on March 14, 2025, led by Yuri Panchul from Samsung Advanced Computing Lab, Silicon Valley.
Β Are you eager to dive into the world of FPGA development and digital design? Join us for an exciting two-day training and hackathon in Armenia, where you’ll get hands-on experience with SystemVerilog, FPGA programming, and even ASIC design using Tiny Tapeout infrastructure!
Day 1: Training β Mastering FPGA Digital Design
The first day is a deep dive into digital design flow for FPGA, covering essential topics such as:
- Introduction to SystemVerilog for hardware description.
- Basics of SystemVerilog hardware description language.
- Hands-on combinational logic exercises using buttons and LEDs.


- Improving proficiency with SystemVerilog syntax by doing exercises with graphics. The students will draw static pictures on a color LCD screen or an HDMI display by changing the SystemVerilog code that computes a color RGB (red/green/blue) using X and y coordinates provided by an LCD or HDMI controller.

Photo from Verilog Meetup events in Mexico and Armenia
- Understand propagation delay, synchronization, clock, D-flip-flop, slack, and aperture.
- Implementing sequential logic and building animated graphics.
- Moving the studentsβ exercises developed on FPGA to Tiny Tapeout infrastructure, the most affordable way to do ASIC design. We will use a special template that allows students to write the same code targeting ASIC and FPGA
π‘ All designs developed during the training will be synthesized on real hardware boards and tested to ensure functionality and performance.Music β Implementing audio processing and sound synthesis.
- Microarchitecture β Exploring processor design and microarchitectural components.
- CPU β Instruction sets, execution pipelines, and CPU architecture.
π‘ All designs developed during the training will be synthesized on real hardware boards and tested to ensure functionality and performance.
Hackathon
π
Date: March 14, 2025
π Location: Armenia Marriot Hotel Yerevan, Armenia
- Project Development β Participants apply their SystemVerilog knowledge to custom projects.
- Q&A
- Project Submission & Presentations β Participants showcase their work.
- Awards & Closing Ceremony β Best projects will be recognized and awarded prizes.